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Xilinx ISE Design Suite v12 4 英文正式版(賽靈思 ISE? 12 設計套件 FPGA/DSP和嵌入式處理系統軟體)(DVD版)

破解說明:
Check /SPYRAL
內容說明:
2010 年 5 月 4 日，中國北京 —— 全球可編程平台領導廠商賽靈思公司（Xilinx, Inc.
(NASDAQ:XLNX) ）日前推出 ISE? 12 軟體設計套件，實現了具有更高設計生產力的功耗和成
本的突破性優化。ISE 設計套件首次利用「智慧」時鐘門控技術，將動態功耗降低多達 30%。
此外，該新型套件還提供了基於時序的高級設計保存功能、為即插即用設計提供符合 AMBA 4
AXI4 規範的 IP 支援，同時具備第四代部分重配置功能的直觀設計流程，可降低多種高性能
應用的系統成本。
英文說明:
Xilinx introduced the ISE?Design Suite 12 software to enable
breakthrough optimizations for power and cost with greater design
productivity. For the first time, ISE design tools deliver 'intelligent'
clock-gating technology that reduces dynamic power consumption by as
much as 30 percent. The new suite also provides advances in
timing-driven design preservation, AMBA 4 AXI4-complaint IP support for
plug-and-play design, and an intuitive design flow with
fourth-generation partial reconfiguration capabilities that lowers
system cost for a broad range of high performance applications.

With full production support for all Xilinx?Virtex?6 and Spartan?6
FPGA families, the ISE 12 release continues its evolution as the
industry's only domain-specific design suite with interoperable design
flows and tool configurations for logic, digital signal processing
(DSP), embedded processing, and system-level design. In addition, Xilinx
incorporated a number of software infrastructure and methodology
enhancements that improve run time, streamline system integration, and
expand IP interoperability across its latest generation device families
and Targeted Design Platforms.

Intelligent Automation for Power Optimization

ISE Design Suite 12 introduces the FPGA industry's first intelligent
clock-gating technology with fully automated analysis and fine-grain
(logic slice) optimization capabilities specifically developed to reduce
the number of transitions, a primary contributing factor of dynamic
power dissipation in digital designs. The technology works by analyzing
designs using a series of unique algorithms to detect sequential
elements...
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